1. Field of the Invention
The present invention relates to a method for programming a memory, and more particularly, to a method for programming a nonvolatile semiconductor memory.
2. Discussion of the Related Art
Generally, nonvolatile semiconductor memories, such as electrically erasable and programmable read-only memories (EEPROMs) and flash EEPROMs, intended as mass storage media possess an excessive cost per bit. A study on a multibit cell has been currently carried out as a method to solve the above-mentioned problem.
The packing density of a nonvolatile memory corresponds with the number of memory cells on a one-to-one basis. A multibit cell stores at least two data bits in a single memory cell, thereby significantly increasing the storage packing density of the data in the same chip area without reducing a memory cell size.
In order to embody the multibit cell, more than three threshold voltage levels must be programmed for each memory cell. For example, in order to store two data bits per cell, respective cells become programmable by four threshold level steps, i.e., 2.sup.2 =4. As a result, the four threshold level steps logically correspond to respective logic states of 00, 01, 10, and 11.
In the above-described multilevel programming, it is critical that respective threshold voltage levels have a statistical distribution of approximately 0.5 V. Consequently, as the distribution decreases by accurately adjusting the respective threshold levels, more levels can be programmed allowing the number of bits per cell to be increased.
To decrease the above voltage distribution, a technique for repeatedly programming and verifying has generally been used in the programming. In this technique, a series of voltage pulses is applied to a cell to program a nonvolatile memory cell at a desired threshold level. A reading process between the respective voltage pulses verifies whether the cell reaches the desired threshold level. During verification, when the verified threshold level value reaches the desired threshold level value, the programming process stops.
In the system for repeatedly programming and verifying, it is difficult to reduce the error distribution of the threshold levels due to a program voltage pulse width. Furthermore, the algorithm of repeatedly programming and verifying requires an additional circuit, thereby increasing the peripheral circuit area of a chip. Moreover, this method increases the programming time.
To eliminate the above-stated drawbacks, R. Cernea of SunDisk Co. introduced a simultaneous programming and verifying technique (U.S. Pat. No. 5,422,842). FIG. 1A shows the symbol and circuit diagram of the EEPROM of Cernea. The EEPROM cell consists of a control gate 1, a floating gate 2, a source 3, a channel region 4, and a drain 5.
When a voltage sufficient to cause programming is applied to control gate 1 and drain 5, a current flows between drain 5 and source 3. The current is compared to a given reference current to generate a programming completion signal when the current is equal to or less than the reference current. This process is illustrated in FIG. 1B.
In this technique, the programming state is automatically verified at the same time as the programming to slightly counteract the drawbacks of repeatedly programming and verification. However, the threshold voltage level applied to control gate 1 of the memory cell is not adjusted.
U.S. Pat. No. 5,043,940 to Harari performs the multilevel programming by changing reference currents corresponding to respective levels. As shown in FIG. 1B, the reference currents for verification are not explicitly or linearly related to the threshold voltages of a cell. Therefore, the multilevel cannot be directly and effectively controlled in the current-controlled method.